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[IC design] Google interview - IC design verification part one

Google recruiter 問了我要不要參加 DV 的面試

但是由於我也有 Digital IC design 的經驗

所以第一關先安排 DIC 的考試

聊了過去的 IC設計與驗證經驗之後

他要求我寫下面這個題目的部分程式碼



module bit_fifo #(parameter N) ( // N is the depth

input clk,

input rst_n,

input [2:0] wcnt,

input [3:0] wdat,

output w_ok,

input [2:0] rcnt,

output [3:0] rdat,

output r_ok

);


1. Data is little endian. Bit FIFO depth = N bits. Use dcnt to represent the current number of bits in FIFO.

2. Can accept concurrent read or write requests of up to 4 bits per cycle.

3. wcnt=0~4; when wcnt==0, no data is written, and w_ok should be 0. w_ok==1 only when the entire amount can be written.

4. rcnt=0~4; when rcnt==0, no data is popped, and r_ok should be 0. r_ok==1 only when the entire amount can be popped


Q1. Can you determine the logic of w_ok and r_ok?

Q2. Can you determine the next-cycle value of dcnt after considering w_ok and r_ok?


在此提供我的解答

Q1.

assign w_ok = ((wcnt == 3’d0) || ((N-dcnt)<wcnt) ) ? 1’b0:1’b1;

assign r_ok = ((rcnt == 4’d0) || (dcnt < rcnt)) ? 1’b0 : 1’b1;


Q2.

assign dcnt_nx = (w_ok) ? ((r_ok) ? (dcnt + wcnt -rcnt): dcnt + wcnt) : ((r_ok) ? dcnt -rcnt: dcnt);


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