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[IC驗證] Add SystemVerilog assertion 極簡範例

SystemVerilog assertion rules 的極簡範例

透過 hook的方式將 dut_checker 掛上 dut

並將dut interface的所有訊號直接對接


module dut_checker(

input clk,

input reset_n

);


AST_FIFO_RD_EMPTY : assert property(

@(posedge clk) disable iff (!reset_n)

dut.fifo_empty |-> ~dut.fifo_read


) else

$display("[Assertion failed] You cannot read fifo when fifo is empty");


endmodule


bind dut dut_checker u_dut_checker(

.*

);


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